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Frequently asked questions
. What does this tool do?
Our AI-powered tool automatically generates RTL documentation, including block diagrams, timing diagrams directly from your RTL code. It ensures that documentation stays accurate and in sync with design updates.
Who can benefit from this tool?
RTL designers, verification engineers, system architects working on ASIC/FPGA design projects will find this tool invaluable for streamlining documentation and improving collaboration.
Does it support all RTL languages?
Currently, the tool supports Verilog and SystemVerilog with plans to expand support for additional HDL languages.
Can the AI model run locally, or does it require a cloud connection?
You can deploy the model locally for privacy and security or run it on a remote server.
Is my design data secure when using remote deployment?
Yes. When running on a remote server, all data transmissions are encrypted. We also provide options for on-premise deployment.
How do I get support if I run into issues?
We provide technical support via live chat.